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DG535/536
Vishay Siliconix
16-Channel Wideband Video Multiplexers
FEATURES
D D D D D D D Crosstalk: -100 dB @ 5 MHz 300 MHz Bandwidth Low Input and Output Capacitance Low Power: 75 mW Low rDS(on): 50 W On-Board Address Latches Disable Output
BENEFITS
D High Video Quality D Reduced Insertion Loss D Reduced Input Buffer Requirements D Minimizes Power Consumption D Simplifies Bus Interface D D D D D D
APPLICATIONS
Video Switching/Routing High Speed Data Routing RF Signal Multiplexing Precision Data Acquisition Crosspoint Arrays FLIR Systems
DESCRIPTION
The DG535/536 are 16-channel multiplexers designed for routing one of 16 wideband analog or digital input signals to a single output. They feature low input and output capacitance, low on-resistance, and n-channel DMOS "T" switches, resulting in wide bandwidth, low crosstalk and high "off" isolation. In the on state, the switches pass signals in either direction, allowing them to be used as multiplexers or as demultiplexers. and a low 75-mW power consumption vastly reduces power supply requirements.
Theses devices are built on a proprietary D/CMOS process which creates low-capacitance DMOS FETs and high-speed, low-power CMOS logic on the same substrate.
On-chip address latches and decode logic simplify microprocessor interface. Chip Select and Enable inputs simplify addressing in large matrices. Single-supply operation
For more information please refer to Vishay Siliconix Application Note AN501 (FaxBack document number 70608).
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG536
GND S8 S7 S6 S5 S4 S3 S2 S1 DIS CS CS EN A0 GND GND GND GND S4 GND S5 GND 1 2 3 4 5 6 7 8 9 10 11 12 Latches/Decoders/Drivers 13 14 Top View Dual-In-Line 16 15 A2 A1
DG535
28 27 26 25 24 23 22 21 20 19 18 17
S9 S10 S11 S12 S13 S14 S15 S16 D V+ ST A3 DIS CS CS EN A0 A1 A2 A3 ST V+ D 7 8 9 10 11 12 13 14 15 16 17
PLCC/Cerquad S1 S2 S3
65432
1 44 43 42 41 40
39 38 37 36 35 Latches/ Decoders/ Drivers 34 33 32 31 30 29
S6 GND S7 GND S8 GND S9 GND S10 GND S11
18 19 20 21 22 23 24 25 26 27 28 S 16 GND S 15 GND S 14 GND S 13 GND S 12 GND GND
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Document Number: 70070 S-02315--Rev. D, 05-Oct-00
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DG535/536
Vishay Siliconix
TRUTH TABLES AND ORDERING INFORMATION ORDERING INFORMATION
Temperature Range
-40 to 85_C _
Package
28-Pin Plastic DIP 44-Pin PLCC 28-Pin Sidebraze 44-Pin Cerquad
Part Number
DG535DJ DG536DN DG535AP DG535AP/883 DG536AM/883
-55 to 125_C 125 C
TRUTH TABLE
EN
0 X X
CS
X 0 X
CS
X X 1
STa
1
A3
X 0 0 0 0 0 0 0 0
A2
X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X
A1
X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X
A0
X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X
Channel Selected
None S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 Maintains previous switch condition
Disableb
High Z
1
1
0
1
1 1 1 1 1 1 1 1
Low Z
X
X
X
0
X
High Z or Low Z
Logic "0" = VAL v 4.5 V Logic "1" = VAH w 10.5 V X = Don't Care Notes: a. Strobe input (ST) is level triggered. b. Low Z, High Z = impedance of Disable Output to GND. Disable output sinks current when any channel is selected.
ABSOLUTE MAXIMUM RATINGS
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +18 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3 V) to (V+ plus 2 V ) or 20 mA, whichever occurs first VS, VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3 V) to V+ plus 2 V) or 20 mA, whichever occurs first Current (any terminal) Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Current (S or D) Pulsed 1 ms 10% duty cycle . . . . . . . . . . . . . . . . . . . . 40 mA Storage Temperature (A Suffix) . . . . . . . . . . . . . . . . . . . . -65 to 150_C (D Suffix) . . . . . . . . . . . . . . . . . . . . -65 to 125_C Notes: a. All leads soldered or welded to PC board. b. Derate 8.6 mW/_C above 75_C. c. Derate 16 mW/_C above 75_C. d. Derate 6 mW/_C above 75_C. e. Derate 11 mW/_C above 75_C. Document Number: 70070 S-02315--Rev. D, 05-Oct-00 28-Pin Sidebrazec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200 mW 44-Pin PLCCd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW 44-Pin Cerquade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW
Power Dissipation (Package)a 28-Pin Plastic DIPb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 mW www.vishay.com
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DG535/536
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Analog Switch
Analog Signal Rangee Drain-Source On-Resistance Resistance Match Source Off Leakage Current Drain On Leakage Current Disable Output VANALOG rDS(on) DrDS(on) IS(off) ID(on) RDISABLE IS = -1 mA, VD = 3 V EN = 10.5 V Sequence Each Switch On VS = 3 V, VD = 0 V, EN = 4.5 V VS = VD = 3 V, EN = 10.5 V IDISABLE = 1 mA, EN = 10.5 V Full Room Full Room Room Full Room Full Room Full 100 -10 -100 -10 -1000 55 0 10 90 120 9 10 100 10 1000 200 250 -10 -100 -10 -100 0 10 90 120 9 10 100 -10 -100 200 250 nA V W
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Symbol
V+ = 15 V, ST, CS = 10.5 V CS = 4.5 V, VA = 4.5 or 10.5 Vf
Tempb
Typc
Minc
Maxc
Minc
Maxc
Unit
W
Digital Control
Input Voltage High Input Voltage Low Address Input Current Address Input Capacitance VAIH VAIL IAI CA VA = GND or V+ Full Full Room Full Full <0.01 -1 -100 10.5 4.5 1 100 -1 -100 10.5 4.5 1 100 mA pF V
5
Dynamic Characteristics
PLCC On State Input Capacitancee CS(on) VD = VS = 3 V Cerquad DIP PLCC Off State Input Capacitancee CS(off) VS = 3 V Cerquad DIP PLCC Off State Output Capacitancee Multiplexer Switching Time Break-Before-Make Interval EN, CS, CS, ST, tON EN, CS, CS, ST, tOFF Charge Injection CD(off) VD = 3 V Cerquad DIP tTRANS tOPEN tON tOFF Q See Figure 4 See Figure 2 and 3 See Figure 2 See Figure 5 RIN = 75 W RL = 75 W f = 5 MHz See Figure 9 RIN = RL = 75 W f = 5 MHz EN = 4.5 V See Figure 8 PLCC Cerquad DIP PLCC Cerquad DIP Room Room Room Room Room Room Room Room Room Full Full Full Full Room Room Room Room Room Room Room -35 -100 -93 -60 -85 -84 -60 dB 25 300 150 32 35 40 2 5 3 8 12 9 300 25 300 150 pC 300 ns 20 20 55 8 55 8 pF 45 45
Single-Channel Crosstalk
XTALK(SC)
Chip Disabled Crosstalk
XTALK(CD)
Document Number: 70070 S-02315--Rev. D, 05-Oct-00
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DG535/536
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Symbol
V+ = 15 V, ST, CS = 10.5 V CS = 4.5 V, VA = 4.5 or 10.5 Vf
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Tempb
Typc
Minc
Maxc
Minc
Maxc
Unit
Dynamic Characteristics (Cont'd)
RIN = 10 W RL = 10 kW W f = 5 MHz See Figure 10 RIN = 10 W RL = 10 kW W f = 5 MHz See Figure 7 PLCC Cerquad DIP PLCC Cerquad DIP Room Room Room Room Room Room Room -92 -87 -72 -74 -74 -60 500 MHz -60 -60 dB
Adjacent Input Crosstalk
XTALK(AI)
All Hostile Crosstalke
XTALK(AH)
Bandwidth
BW
RL = 50 W , See Figure 6
Power Supplies
Positive Supply Current Supply Voltage Range I+ V+ Any One Channgel Selected with All Logic Inputs at GND or V+ Room Full Full 5 10 50 100 16.5 10 50 100 16.5 mA V
Minimum Input Timing Requirements
Strobe Pulse Width A0, A1, A2, A3 CS, CS, EN Data Valid to Strobe A0, A1, A2, A3 CS, CS, EN Data Valid after Strobe tSW tDW tWD See Figure 1 Full Full Full 200 100 50 200 100 50 ns
Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VA = input voltage to perform proper function.
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
rDS(on) vs. VD and Temperature
r DS(on) Drain-Source On-Resistance ( W ) - V+ = +15 V GND = 0 V
400 r DS(on) Drain-Source On-Resistance ( W ) - 360 320 280 240 200 160 120 80 40 0 0
300 270 240 210 180
rDS(on) vs. VD and Power Supply Voltage
GND = 0 V TA = 25_C
8V 12 V
125_C
150 120 90 60 30 0
15 V
25_C -55_C
2
4
6
8
10
0
2
4
6
8
10
VD - Drain Voltage (V)
VD - Drain Voltage (V)
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Document Number: 70070 S-02315--Rev. D, 05-Oct-00
DG535/536
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Logic Input Switching Threshold vs. Supply Voltage (V+)
10 9 8 7 I+ ( m A) V th (V) 6 5 4 3 2 2 1 0 8 10 12 14 16 18 V+ - Positive Supply (V) 0 10 11 12 13 14 15 16 17 18 V+ - Positive Supply (V) GND = 0 V TA = 25_C 14 12 10 125_C 8 25_C 6 4 -55_C GND = 0 V
Supply Current vs. Supply Voltage and Temperature
1 mA 100 nA
ID(on) vs. Temperature
1 mA V+ = +15 V GND = 0 V VD = VS = 3 V I S, I D - Leakage 100 nA
Leakage Current vs. Temperature
V+ = +15 V GND = 0 V ID(off) IS(off) 1 nA
I D(on) - Leakage
10 nA
10 nA
1 nA
100 pA
100 pA
10 pA
10 pA
1 pA -55 -35 -15 5 25 45 65 85 105 125
1 pA -55 -35 -15 5 25 45 65 85 105 125 Temperature (_C) Temperature (_C)
Adjacent Input Crosstalk vs. Frequency
-120 DG536 RIN = 10 W -4 0
-3 dB Bandwidth Insertion Loss vs. Frequency
-100
DG536 X TALK(AI) (dB) -80 DG536 RIN = 75 W Insertion Loss (dB) -8 -3 dB Points -12 Test Circuit See Figure 6 RL = 50 W
-60 DG535 RIN = 10 W
-40
-16 -20 Test Circuit See Figure 10 -20 0.1 1 10 100 1
DG535
0 f - Frequency (MHz)
10
100
1000
f - Frequency (MHz)
Document Number: 70070 S-02315--Rev. D, 05-Oct-00
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DG535/536
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Chip Disable Crosstalk vs. Frequency
-160 -140 -120 X TALK(CD) (dB) X TALK(AH) (dB) -100 -80 -60 -40 -20 0 0.1 1 10 100 f - Frequency (MHz) DG535 RL = 75 W Test Circuit See Figure 8 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 f - Frequency (MHz) DG535 RIN = 10 W RL = 10 kW Test Circuit See Figure 7 DG536 RIN = 10 W RL = 10 kW DG536 RIN = 75 W RL = 75 W
All Hostile Crosstalk vs. Frequency
DG536 RL = 75 W
DG536 RL = 50 W
tON, tOFF and Break-Before-Make vs. Temperature
160 140 120 Switching Time (ns) X TALK(SC) (dB) 100 80 60 40 20 0 -55 -35 -15 5 25 45 65 85 105 125 Temperature (_C) tOFF Test Circuit See Figures 2, 3, 4 tON
Single Channel Crosstalk vs. Frequency
-160 -140 -120 -100 DG536 -80 -60 DG535 -40 -20 0 0.1 1 10 100 f - Frequency (MHz) Test Circuit See Figure 9 RIN = 75 W RL = 75 W
tBBM
INPUT TIMING REQUIREMENTS
15 V ST 0V tSW tDW 15 V 10.5 V CS, A0, A1, A2, A3 CS, EN 4.5 V 0V 4.5 V 10.5 V tWD 7.5 V
FIGURE 1.
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DG535/536
Vishay Siliconix
TEST CIRCUITS
+15 V +15 V Address Logic Input tr <20 ns tf <20 ns S16 S1 - S15 90% D 1 kW 35 pF VO Signal Output +3 V CS 15 V 50% 0V EN or CS
Logic Input
ST A0 A1 A2 A3
V+
EN or CS CS GND
tON
tOFF
FIGURE 2. EN, CS, CS, Turn On/Off Time
+15 V
+15 V
V+ EN, CS A1, A2, A3 Address Input Logic Input A0 ST GND CS
Address Logic Input tr <20 ns tf <20 ns S1 +3 V
15 V 0V 15 V 0V
50%
S2 - S15
D 1 kW 35 pF
VO
VOUT
tON(ST) 90%
0V
FIGURE 3. Strobe ST Turn On Time
+15 V
+15 V
+3 V Address Logic Input tr <20 ns tf <20 ns 15 V 50% 0V Switch Output S1 Turning Off D VO tBBM 1 kW 35 pF tTRANS 90% S16 Turning On
V+ EN CS ST A0 A1 A2 A3 S1 S16 S2 thru S15
GND
CS
FIGURE 4. Transition Time and Break-Before-Make Interval
Document Number: 70070 S-02315--Rev. D, 05-Oct-00
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DG535/536
Vishay Siliconix
TEST CIRCUITS
+15 V +15 V V+ A0, A1, A2, A3 S16 CS GND CS EN CS ST CS Signal Generator (75 W) S1 A0 to A3 V+ S2 thru S15 ST EN +3 V Logic Input D VO CL 1000 pF +15 V +15 V +15 V
D RL 50 W
VO
GND
CS
VOUT
DVOUT
DVOUT is the measured voltage error due to charge injection. The charge injection in Coulombs is Q = CL x DVOUT
FIGURE 5. Charge Injection
FIGURE 6. Bandwidth
Channel 1 On S1 S1 S2 RIN S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 V VO V RL VO S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 V
All Channels Off
VO
RL
X TALK(AH) + 20 log 10
X TALK(CD) + 20 log10
VO V
FIGURE 7. All Hostile Crosstalk
FIGURE 8. Chip Disabled Crosstalk
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Document Number: 70070 S-02315--Rev. D, 05-Oct-00
DG535/536
Vishay Siliconix
TEST CIRCUITS
Channel 1 On S1 S2 RIN S3 S4 S5 S6 S7 S8 S9 S10 V S11 S12 S13 S14 S15 S16 Notes: 1. Any individual channel between S2 and S16 can be selected 2. X TALK(SC) + 20 log10 VO V is scanned sequentially from S 2 to S 16 X TALK(AI) + 20 log10 V Sn - 1 V Sn or 20 log10 V Sn ) 1 V Sn RL VO VSn+1 RIN 10 W Sn+1 RL 10 kW VSn Sn RIN 10 W
VSn-1 Sn-1
FIGURE 9. Single Channel Crosstalk
FIGURE 10. Adjacent Input Crosstalk
PIN DESCRIPTION
Symbol
S1 thru S16 D DIS CS, CS, EN A0 thru A3 ST V+ GND Analog inputs/outputs Multiplexer output/demultiplexer input Open drain low impedance to analog ground when any channel is selected Logic inputs to selected desired multiplexer(s) when using several multiplexers in a system Binary address inputs to determine which channel is selected Strobe input that latches A0, A1, A2, A3, CS, CS, EN Positive supply voltage input Analog signal ground and most negative potential All ground pins should be connected externally to ensure dynamic performance
Description
Document Number: 70070 S-02315--Rev. D, 05-Oct-00
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DG535/536
Vishay Siliconix
DETAILED DESCRIPTION
The DG535/536 are 16-channel single-ended multiplexers with on-chip address logic and control latches. The multiplexer connects one of sixteen inputs (S1, S2 through S16) to a common output (D) under the control of a 4-bit binary address (A0 to A3). The specific input channel selected for each address is given in the Truth Table. All four address inputs have on-chip data latches which are controlled by the Strobe (ST) input. These latches are transparent when Strobe is high but they maintain the chosen address when Strobe goes low. To facilitate easy microprocessor control in large matrices a choice of three independent logic inputs (EN, CS and CS) are provided on chip. These inputs are gated together (see Figure 11) and only when EN = CS = 1 and CS = 0 can an output switch be selected. This necessary logic condition is then latched-in when Strobe (ST) goes low.
Signal IN Signal OUT
SW1
SW3
SW2
Signal GND
FIGURE 12. "T" Switch Arrangement
The two second level series switches further improve crosstalk and help to minimize output capacitance. The DIS output can be used to signal external circuitry. DIS is a high impedance to GND when no channel is selected and a low impedance to GND when any one channel is selected.
CS Latch A0 Latch A1 Latch A2 Latch A3 Latch ST Decode Logic
CS
The DG535/536 have extensive applications where any high frequency video or digital signals are switched or routed. Exceptional crosstalk and bandwidth performance is achieved by using n-channel DMOS FETs for the "T" and series switches.
EN
Gate Source
Drain
FIGURE 11.CS, CS, EN, ST Control Logic
Break-before-make switching prevents momentary shorting when changing from one input to another. The devices feature a two-level switch arrangement whereby two banks of eight switches (first level) are connected via two series switches (second level) to a common DRAIN output. In order to improve crosstalk all sixteen first level switches are configured as "T" switches (see Figure 12). With this method SW2 operates out of phase with SW1 and SW3. In the on condition SW1 and SW3 are closed with SW2 open whereas in the off condition SW1 and SW3 are open and SW2 closed. In the off condition the input to SW3 is effectively the isolation leakage of SW1 working into the on-resistance of SW2 (typically 200 W).
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It can clearly be seen from Figure 13 that there exists a PN junction between the substrate and the drain/source terminals. Should a signal which is negative with respect to the substrate (GND pin) be connected to a source or drain terminal, then the PN junction will become forward biased and current will flow between the signal source and GND. This effective shorting of the signal source to GND will not necessarily cause any damage to the device, provided that the total current flowing is less than the maximum rating, (i.e., 20 mA).
Document Number: 70070 S-02315--Rev. D, 05-Oct-00
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EEEEEEEEEEEEEE EEEEEEEEEEEEEE
n+ p n+ p- Substrate GND
FIGURE 13. Cross-Section of a Single DMOS Switch
DG535/536
Vishay Siliconix
DETAILED DESCRIPTION
Since no PN junctions exist between the signal path and V+, positive overvoltages are not a problem, unless the breakdown voltage of the DMOS drain terminal (see Figure 13) (+18 V) is exceeded. Positive overvoltage conditions must not exceed +18 V with respect to the GND pin. If this condition is possible (e.g. transients in the signal), then a diode or Zener clamp may be used to prevent breakdown. being coupled back to the analog signal source and C2 blocks the dc bias from the output signal. Both C1 and C2 should be tantalum or ceramic disc type capacitors in order to operate efficiently at high frequencies. Active bias circuits are recommended if rapid switching time between channels is required.
The overvoltage conditions described may exist if the supplies are collapsed while a signal is present on the inputs. If this condition is unavoidable, then the necessary steps outlined above should be taken to protect the device
An alternative method is to offset the supply voltages (see Figure 15).
DC Biasing
Decoupling would have to be applied to the negative supply to ensure that the substrate is well referenced to signal ground. Again the capacitors should be of a type offering good high frequency characteristics.
To avoid negative overvoltage conditions and subsequent distortion of ac analog signals, dc biasing may be necessary. Biasing is not required, however, in applications where signals are always positive with respect to the GND or substrate connection, or in applications involving multiplexing of low level (up to "200 mV) signals, where forward biasing of the PN substrate-source/drain terminals would not occur.
Level shifting of the logic signals may be necessary using this offset supply arrangement.
+12 V Analog Signal IN V+
S
DG536
D
Analog Signal OUT
Biasing can be accomplished in a number of ways, the simplest of which is a resistive potential divider and a few dc blocking capacitors as shown in Figure 14.
Decoupling Capacitors +15 V
GND
+
-3 V
Analog Signal IN
C1 +
R1 S R2 V+ + C2 D Analog Signal OUT
FIGURE 15. DG536 with Offset Supply
100 mF/16 V Tantalum
DG536
GND
100 mF/16 V Tantalum
TTL to CMOS level shifting is easily obtained by using a MC14504B.
Circuit Layout
FIGURE 14. Simp le Bias Circuit
R1 and R2 are chosen to suit the appropriate biasing requirements. For video applications, approximately 3 V of bias is required for optimal differential gain and phase performance. Capacitor C1 blocks the dc bias voltage from
Document Number: 70070 S-02315--Rev. D, 05-Oct-00
Good circuit board layout and extensive shielding is essential for optimizing the high frequency performance of the DG536. Stray capacitances on the PC board and/or connecting leads will considerably degrade the ac performance. Hence, signal paths must be kept as short as practically possible, with extensive ground planes separating signal tracks.
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